1. Field of the Invention
The present invention relates to a data processing system having a floating point arithmetic unit and, more particularly, to a method and apparatus for performing quad precision floating point arithmetic operations on hardware implemented for less than quad precision.
2. Description of the Related Art
The arrival of computers has revolutionized the capabilities to perform complex numerical calculations rapidly. For example, before the availability of computers, weather forecasting was a practical impossibility. While theoretically possible, such forecasting requires many computations and, therefore, without the use of computers, takes so much time as to make the forecasts obsolete long before the computations could be finished. However, the availability of computers has made certain computations, such as weather forecasting, possible which without computers would have been impractical.
Nevertheless, even with early computers, some calculations were too time-consuming to be practical. Other calculations, even if executable at sufficiently high speeds on special purpose computers, would be too slow on general purpose computers. However, with improvement in microprocessor performance, many more types of calculations can be executed in a reasonable amount of time. During the late 1980's, the performance of microprocessor-based machines improved at a rate of between 1.5 and two times per year. It is likely that this trend will continue. It is therefore now possible to carry out computations that only a few years ago would have been excessively slow or only possible on supercomputers and other special purpose computers.
Many time-consuming calculations are iterative procedures. Iterative procedures are prone to inaccurate results because of accumulation of round-off error. In floating point arithmetic every calculation may introduce a certain amount of round-off error. A small loss of precision due to round-off error may grow to a large inaccuracy after several iterations.
One example of round-off error is the effect of representing irrational numbers in a fixed number of bits. The degree of accuracy in a final result is proportional to the number of digits of significand used for intermediate results. Because modern architectures make highly iterative procedures feasible, it is desirable to maintain the accuracy of the results of those procedures by allowing their intermediate results to be stored in a format having many digits of significand.
An additional motivation for long significands is the problem of arithmetic operations involving quantities of vastly differing magnitudes, e.g., the addition of a very small quantity to a very large quantity. Procedures for floating point addition usually align the significand of each operand so that both quantities have the same exponent. This step is followed by adding the significands. Next, if the significand addition results in an overflow, the procedure increments the exponent of the result. The significand alignment procedure requires shifting one (or both) significand(s). Shifting a significand may cause some bits of the significand to be lost. Such losses result from shifting the significand beyond the field available for significand storage. Therefore, it is desirable to allow larger significands by extending the range within which shifts may be made without an excessive loss of precision.
IEEE standard 754 specifies a fraction field of 23 bits for single precision and a fraction field of 52 bits for double precision. These formats correspond to approximately seven and sixteen significant decimal digits, respectively. There are calculations that are inaccurate even when using double precision. Therefore, it is desirable to provide means for yet higher precision floating point calculations.
It is possible to build hardware for quad precision, but such hardware is not generally desirable. Quad precision hardware would require 128-bit wide data paths and arithmetic logic units. These data paths and large ALUs use area on micro processor chips that could be used for other functions. Furthermore, wider data paths and ALUs take up larger chip areas, and wider data paths and ALUs imply longer execution delays. While for some calculations quad precision is either desirable or necessary, for other calculations double precision or single precision is adequate. Because of the wider data paths on true quad precision processors, the double and single precision calculations would be slower on such hardware than on single and double precision hardware.
It is therefore desirable to provide for fast quad precision calculations without unduly slowing double and single precision calculations.
It is possible to provide for quad precision calculations on double precision hardware without modification to the hardware. However, such implementations are undesirably slow because they rely heavily on software for carrying out quad precision calculations.
Thus, there is a need for an improved technique for allowing high precision calculations without slowing lower precision calculations.